Datasheet

t
r(ETM)
t
h(ETM)
t
l(ETM)
t
f(ETM)
t
cyc(ETM)
147
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.22.8 Embedded Trace Macrocell (ETM-R5)
The device contains a ETM-R5 module with a 32-bit internal data port. The ETM-R5 module is connected
to a Trace Port Interface Unit (TPIU) with a 32-bit data bus. The TPIU provides a 35-bit (32-bit data, 3-bit
control) external interface for trace. The ETM-R5 is CoreSight compliant and follows the ETM v3
specification. For more details, see the ARM CoreSight ETM-R5 TRM specification.
6.22.8.1 ETM TRACECLKIN Selection
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN terminal. The
selection is chosen by the EXTCTLOUT[1:0] control bits of the TPIU (default is '00'). The address of this
register is the TPIU base address + 0x404.
Before the user begins accessing TPIU registers, the TPIU should be unlocked through the CoreSight key
and 1 or 2 written to this register.
Table 6-55. TPIU / TRACECLKIN Selection
EXTCTLOUT[1:0] TPIU/TRACECLKIN
00 Tied-zero
01 VCLK
10 ETMTRACECLKIN
11 Tied-zero
6.22.8.2 Timing Specifications
Figure 6-30. ETMTRACECLKOUT Timing
Table 6-56. ETMTRACECLK Timing
PARAMETER MIN MAX UNIT
t
cyc(ETM)
Clock period 18.18 ns
t
l(ETM)
Low pulse width 6 ns
t
h(ETM)
High pulse width 6 ns
t
r(ETM)
Clock and data rise time 3 ns
t
f(ETM)
Clock and data fall time 3 ns