Datasheet

Write to SPIDAT0 (SLAVE)
Write to SPIDAT1
SPICLK
SPISIMO
SPISOMI
SPIENA
SPISCS
Write to SPIDAT1
Write to SPIDAT0 (SLAVE)
WORD1 WORD2
CSHOLD = 1 CSHOLD = 0
Basic Operation www.ti.com
27.2.6.5.2.1 CSHOLD Bit in Master Mode
Each word in a master-mode SPI can be individually initialized for one of the two modes via the CSHOLD
bit in its control field.
If the CSHOLD bit is set in the control field of a word, the chip select signal will not be deactivated until the
next control field is loaded with new chip select information. Since the chip-select is maintained active
between two transfers, the chip-select hold delay (T2CDELAY) is not applied at the end of the current
transaction, and the chip-select set-up time delay (C2TDELAY) is not applied as well at the beginning of
the following transaction. However, the wait delay (WDELAY) will be still applied between the two
transactions, if the WDEL bit is set within the control field.
Figure 27-21 shows the SPI pins when a master-mode SPI transfers a word that has its CSHOLD bit set.
The chip-select pins will not be deasserted after the completion of this word. If the next word to transmit
has the same chip-select number (CSNR) value, the chip select pins will be maintained until the
completion of the second word, regardless of whether the CSHOLD bit is set or not.
Figure 27-21. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI)
27.2.6.5.2.2 CSHOLD Bit in Slave Mode (Multi-buffered Mode)
If the CSHOLD bit in a buffer is set to 1, then the MibSPI does not wait for the SPISCS pins to be de-
activated at the end of the shift operation to copy the received data to the receive RAM. With this feature,
it is possible for a slave in multi-buffer mode to do multiple data transfers without requiring the SPISCS
pins to be deasserted between two buffer transfers.
If the CSHOLD bit in a buffer is cleared to 0 in a slave MibSPI, even after the shift operation is done, the
MibSPI waits until the SPISCS pin (if functional) is deasserted to copy the received data to the RXRAM.
If the CSHOLD bit is maintained as 0 across all the buffers, then the slave in multi-buffer mode requires its
SPISCS pins to be deasserted between any two buffer transfers; otherwise, the Slave SPI will be unable
to respond to the next data transfer.
NOTE: In compatibility mode, the slave does not require the SPISCS pin to be deasserted between
two buffer transfers. The CSHOLD bit of the slave will be ignored in compatibility mode.
1244
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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