Datasheet

SCS
ENA
CLK
SOMI
1
t
SCS
CLK
SOMI
VCLK
t
T2CDELAY
Basic Operation www.ti.com
27.2.6.4.2 Transmit-End-to-Chip-Select-Inactive-Delay (T2CDELAY)
T2CDELAY is used in master mode only. It defines a hold time for the slave device that delays the chip
select deactivation by a multiple of VBUSPCLK cycles after the last bit is transferred. T2CDELAY can be
configured between 2 and 256 VBUSPCLK cycles.
The hold time value is calculated as:
t
T2CDELAY
= (T2CDELAY +1) × VCLK Period
Figure 27-18 is the timing diagram when T2CDELAY of 4 VCLK Cycles.
Figure 27-18. Example: t
T2CDELAY
= 4 VCLK Cycles
27.2.6.4.3 Transmit-Data-Finished-to-ENA-Pin-Inactive-Time-Out (T2EDELAY)
T2EDELAY is used in master mode only. It defines a time-out value as a multiple of SPI clock before the
ENAble signal has to become inactive and after the CS becomes inactive. The SPI clock depends on
which data format is selected. If the slave device is missing one or more clock edges, it is becoming de-
synchronized. Although the master has finished the data transfer the
The T2EDELAY defines a time-out value that triggers the DESYNC flag, if the ENA signal isn’t deactivated
in time. DESYNC flag is set to indicate that the Slave device did not deassert its SPIENA pin in time to
acknowledge that it has received all the bits of the sent character.
The timeout value is calculated as:
t
T2EDELAY
= T2EDELAY/SPIclock
Figure 27-19. Transmit-Data-Finished-to-ENA-Inactive-Timeout
NOTE: If T2CDELAY is programmed a non-zero value, then T2EDELAY will start only after the
T2CDELAY completes. This should be taken into consideration to determine an optimum
value of T2EDELAY.
1242
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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