Datasheet
SCS
CLK
SOMI
VCLK
t
C2TDELAY
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Basic Operation
27.2.6.3 Decoded and Encoded Chip Select (Master Only)
In this device the SPI can connect to up to 4 individual slave devices using chip-selects by routing one
wire to each slave. The 4 chip selects in the control field are directly connected to the 4 pins. The default
value of each chip select (not active) can be configured via the register CSDEF. During a transmission,
the value of the chip select control field (CSNR[7:0]) of the SPIDAT1 register (SPIDAT1[23:16]) is driven
on the SPISCS [4:0] pins. When the transmission finishes the default chip-select value (defined by the
CSDEF register) is put on the SPISCS [4:0] pins.
The SPI can support more than 4 slaves by using encoded chip selects. To connect the SPI with encoded
slaves devices, the CSNR field allows multiple active SPISCS pins at the same time, which enables binary
encoded chip selects from 0 to 16. To use encoded chip selects, all four chip select lines have to be
connected to each slave device and each slave needs to have a unique chip-select address. The CSDEF
register is used to provide the address at which slaves devices are all de-selected.
Users can combine decoded and encoded chip selects. For example, n SPISCS pins can be used for
encoding a n-bit address and the remaining pins can be connected to decoded-mode slaves.
27.2.6.4 Chip Select Timing Control
This section describes few fields of the contrlol register SPIDELAY this register decides the chip select
and timing control for the device
27.2.6.4.1 Chip-Select-Active-to-Transmit-Start-Delay (C2TDELAY)
C2TDELAY is used in master mode only. It defines a setup time for the slave device that delays the data
transmission from the chip select active edge by a multiple of VBUSPCLK cycles. ChipSelect-active-to-
transmission delays between 2 to 257 VBUSPCLK cycles can be achieved.
The setup time value is calculated as:
t
C2TDELAY
= (C2TDELAY + 2) × VCLK Period
Figure 27-17 is the timing diagram when C2TDELAY of 8 VCLK Cycles.
Figure 27-17. Example: t
C2TDELAY
= 8 VCLK Cycles
1241
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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