Datasheet

4 3 2 1 0 4 3
0
12
4 3 2 1 0 4 3 012
Master SPI
Int. flag
Slave SPI
Int. flag
SPISOMI
from slave
SPISIMO
from master
Clock polarity = 1
Clock phase = 1
SPISCS
SPICLK signal options:
SPIENA
Clock polarity = 1
Clock phase = 0
Clock polarity = 0
Clock polarity = 0
Clock phase = 0
Clock phase = 1
Basic Operation www.ti.com
27.2.6.2.1 Data Transfer Example
Figure 27-16 illustrates a SPI data transfer between two devices using a character length of five bits.
Figure 27-16. Five Bits per Character (5-Pin Option)
1240
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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