Datasheet

Data is output one-half cycle before the first rising edge of SPICLK and on subsequent falling edges of SPICLK
Input data is latched on the rising edge of SPICLK
Write SPIDAT
SPISIMO
SPISOMI
receive sample
MSB
D6 D5 D4 D3 D2 D1
LSB
D6 D5 D4 D3 D2 D1
D7
1
2
3 4 5 6 7 8
D0
SPICLK
Data is output on the rising edge of SPICLK.
Input data is latched on the falling edge of SPICLK.
Write SPIDAT
SPICLK
SPISIMO
receive sample
MSB
D6 D5 D4 D3 D2 D1
D0
LSB
D6 D5 D4 D3 D2 D1
D7
1
2
3 4
5
6 7 8
SPISOMI
Basic Operation www.ti.com
27.2.6.2 Clocking Modes
SPICLK may operate in four different modes, depending on the choice of phase (delay/no delay) and the
polarity (rising edge/falling edge) of the clock.
The data input and output edges depend on the values of both POLARITY and PHASE as shown in
Table 27-3.
Table 27-3. Clocking Modes
POLARITY PHASE Action
0 0 Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
0 1 Data is output one half-cycle before the first rising edge of SPICLK and on subsequent
falling edges. Input data is latched on the rising edge of SPICLK.
1 0 Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
1 1 Data is output one half-cycle before the first falling edge of SPICLK and on subsequent
rising edges. Input data is latched on the falling edge of SPICLK.
Figure 27-12 to Figure 27-15 illustrate the four possible configurations of SPICLK corresponding to each
mode. Having four signal options allows the SPI to interface with many different types of serial devices.
Figure 27-12. Clock Mode with Polarity = 0 and Phase = 0
Figure 27-13. Clock Mode with Polarity = 0 and Phase = 1
1238
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
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