Datasheet

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1461

Master

Slave

(Master = 1; CLKMOD = 1)

(Master = 0; CLKMOD = 0)

SPIDAT1 SPIDAT0

MSB

LSB

MSB

LSB

Write to

SPIDAT1

SPISOMI

SPISIMO

SPISOMI

SPISIMO

SPICLK

SPISCS

Write to

SPIDAT0

Write to SPIDAT0 (SLAVE)

Write to SPIDAT1 (MASTER)

SPISIMO

SPISOMI

SPIENA

SPISCS

SPICLK

Basic Operation

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27.2.5.3 Five-Pin Operation (Hardware Handshaking)

Five-pin operation combines the functionality of three-pin mode, plus the enable pin and one or more chip

select pins. The result is full hardware handshaking. To use this mode, both the SPIENA pin and the

required number of SPISCS [3:0] pins must be configured as functional pins.

If the SPIENA pin is in high-z mode (ENABLE_HIGHZ = 1), the slave SPI will put this signal into the high-

impedance state by default. The slave will drive the signal SPIENA low when new data is written to the

slave shift register and the slave has been selected by the master (SPISCS is low).

If the SPIENA pin is in push-pull mode (ENABLE_HIGHZ = 0), the slave SPI drives this pin high by default

when it is in functional mode. The slave SPI will drive the SPIENA signal low when new data is written to

the slave shift register (SPIDAT0/SPIDAT1) and the slave is selected by the master (SPISCS is low). If the

slave is deselected by the master (SPISCS goes high), the slave SPIENA signal is driven high.

NOTE: Push-pull mode of the SPIENA pin can be used only when there is a single slave in the

system. When multiple SPI slave devices are connected to the common SPIENA pin, all of

the slaves should configure their SPIENA pins in high-Z mode.

In master mode, if the SPISCS pins are configured as functional pins, then the pins will be in output mode.

A write to the master’s SPIDAT1/SPIDAT0 register will automatically drive the SPISCS signals low. The

master will drive the SPISCS signals high again after completing the transfer of the bits of the data.

In slave mode (CLKMOD = 0), the SPISCS pins will act as SPI functional inputs.

Figure 27-9. SPI Five-Pin Option with SPIENA and SPISCS

1236

Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014

Option (MibSPIP)

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