Datasheet

Master
Slave
(Master = 1; CLKMOD = 1)
(Master = 0; CLKMOD = 0)
SPIDAT1 SPIDAT0
MSB
LSB MSB
LSB
Write to SPIDAT1
SPISOMI
SPISOMI
SPISIMO
SPICLK
SPICLK
SPISCS
SPISCS
Write to SPIDAT1
SPICLK
SPISIMO
SPISOMI
SPICSCS
Basic Operation www.ti.com
27.2.5.2 Four-Pin Mode with Chip Select
The three-pin option and the four-pin options of the SPI / MibSPI are identical in the master mode
(CLKMOD = 1), except that the four-pin option uses either SPIENA or SPISCS [7:0] pins. The I/O
directions of these pins are determined by the CLKMOD control bit as SPI / MibSPI and not general
purpose I/O.
27.2.5.2.1 Four-Pin Option with SPISCS
In master mode, each chip select signal is used to select a specific slave. In slave mode, chip select
signal is used to enable/disable the transfer. Chip-select functionality is enabled by setting one of the
SPISCS [7:0] pins as chip selects. It is disabled by setting all SPISCS [7:0] pins as GIOs in SPIPC0[3:0]
27.2.5.2.1.1 Multiple Chip Selects
The SPISCS [7:0] pins that are used must be configured as functional pins in the SPIPC0[7:0] register.
The default pattern to be put on the SPISCS [7:0] when all the slaves are deactivated is set in the SPIDEF
register. This pattern allows different slaves with different chip-select polarity to be activated by the
SP/MibSPI.
The master-mode SPI is capable of driving either 0 or 1 as the active value for any SPISCS[3:0] output
pin. The drive state for SPISCS[7:0] pins is controlled by the CSNR field of SPIDAT1. The pattern that is
driven will select the slave to which the transmission is dedicated.
In slave mode, the SPI can only be selected by an active value of 0 on any of its selected SPISCS input
pin.
Figure 27-7. Operation with SPISCS
1234
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin SPNU562–May 2014
Option (MibSPIP)
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated