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– Configurable number of ChipSelects
In Multi-buffer Mode, in addition to the above, many other features are configurable
– Number of buffers for each peripheral(or data source/destination, up to 256 buffers supported) or
group(up to 8 groupings)
– Number of DMA controlled buffers & number of DMA request channels(up to 8 for each of transmit
& receive)
– Triggers for each groups, trigger types, trigger sources for individual groups(up to 14 external
trigger sources & 1 internal trigger source)
– Number of DMA transfers for each buffer(up to 65536 for up to 8 buffers)
– Un-interrupted DMA buffer transfer(NOBREAK buffer).
NOTE: SIMO - Slave In Master Out Pin
SOMI - Slave Out Master In Pin
CS - SPI Chip Select Pin
ENA - SPI Enable Pin.
27.1.2 Pin Configurations
The SPI supports data connections as shown in Table 27-1.
Table 27-1. Pin Configurations
Pin Master Mode Slave Mode
SPICLK Drives the clock to external devices Receives the clock from the external master
SPISOMI Receives data from the external slave Sends data to the external master
SPISIMO Transmits data to the external slave Receives data from the external master
SPIENA SPIENA disabled: SPIENA enabled: SPIENA disabled: SPIENA enabled:
GIO Receives ENA signal from GIO Receives ENA signal from
the external slave the external master
SPICS[7:0] SPICS disabled: SPICS enabled: SPICS disabled: SPICS enabled:
GIO Selects one or more slave GIO Receives the CS signal
devices from the external master
NOTE:
1. When the SPICS[3:0] signals are disabled, the chip-select field in the transmit data is
not used.
2. When the SPIENA signal is disabled, the SPIENA pin is ignored in master mode, and
not driven as part of the SPI transaction in slave mode.
1225
SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
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