Datasheet

Chapter 27

SPNU562–May 2014

Multi-Buffered Serial Peripheral Interface Module (MibSPI)

with Parallel Pin Option (MibSPIP)

This chapter provides the specifications for a 16-bit configurable synchronous multi-buffered multi-pin

serial peripheral interface (MibSPI). This chapter also provides the specifications for MibSPI with Parallel

Pin Option (MibSPIP). The MibSPI is a programmable-length shift register used for high-speed

communication between external peripherals or other microcontrollers.

Throughout this chapter, all references to SPI also apply to MibSPI/MibSPIP, unless otherwise noted.

NOTE: This chapter describes a superset implementation of the MibSPI/SPI modules that includes

features and functionality that may not be available on some devices. Device-specific content

that should be determined by referencing the datasheet includes DMA functionality, MibSPI

RAM size, number of transfer groups, number of chip selects, parallel mode support, and

availability of 5-pin operation (SPInENA).

Topic ........................................................................................................................... Page

27.1 Overview........................................................................................................ 1224

27.2 Basic Operation.............................................................................................. 1226

27.3 Control Registers............................................................................................ 1261

27.4 Multi-buffer RAM............................................................................................. 1327

27.5 Parity\ECC Memory ......................................................................................... 1333

27.6 MibSPI Pin Timing Parameters ......................................................................... 1338

1223

SPNU562–May 2014 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin

Option (MibSPIP)

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