Datasheet

www.ti.com DCAN Control Registers
26.17.27 IF3 Observation Register (DCAN IF3OBS)
The IF3 register set can automatically be updated with received message objects without the need to
Initiate the transfer from Message RAM by CPU (Additional information can be found in Section 26.5.1).
The observation flags (Bits [4:0]) in the IF3 Observation register are used to determine, which data
sections of the IF3 Interface Register set have to be read in order to complete a DMA read cycle. After all
marked data sections are read, the DCAN is enabled to update the IF3 Interface Register set with new
data.
Any access order of single bytes or half-words is supported. When using byte or half-word accesses, a
data section is marked as completed, if all bytes are read.
NOTE: If IF3 Update Enable is used and no Observation flag is set, the corresponding message
objects will be copied to IF3 without activating the DMA request line and without waiting for
DMA read accesses.
A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables
updating of IF3 Interface Register set with new data. To avoid data inconsistency, the DMA controller
should be disabled before reconfiguring IF3 observation register.
The status of the current read-cycle can be observed via status flags (Bits [12:8]).
If an interrupt line is available for IF3, an interrupt will be generated by IF3Upd flag. See the device data
sheet to find out if this interrupt source is available
With this, the observation status bits and the IF3Upd bit could be used by the application to realize the
notification about new IF3 content in polling or interrupt mode.
Figure 26-68. IF3 Observation Register (DCAN IF3OBS) [offset = 140h]
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 5 4 3 2 1 0
IF3Upd Reserved IF3SDB IF3SDA IF3SC IF3SA IF3SM Reserved Data B Data A Ctrl Arb Mask
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read; -n = value after reset
Table 26-28. IF3 Observation Register (DCAN IF3OBS) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 These bits are always read as 0. Writes have no effect.
15 IF3 Upd IF3 Update Data
0 No new data has been loaded since IF3 was last read
1 New data has been loaded since IF3 was last read
14-13 Reserved 0 These bits are always read as 0. Writes have no effect
12 IF3 SDB IF3 Status of Data B read access
0 All Data B bytes are already read or are not marked to be read
1 Data B section still has data to read
11 IF3 SDA IF3 Status of Data A read access
0 All Data A bytes are already read or are not marked to be read
1 Data A section still has data to read
10 IF3 SC IF3 Status of Control bits read access
0 All Control section bytes are already read or are not marked to be read
1 Control section still has data to read
1213
SPNU562–May 2014 Controller Area Network (DCAN) Module
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