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DCAN Control Registers

26.17.19 Message Valid X Register (DCAN MSGVAL X)

With the Message Valid X Register, the CPU can detect if one or more bits in the different Message Valid

Registers are set. Each bit of this register represents a group of eight message objects. If at least one of

the MsgVal bits of these message objects are set, the corresponding bit in the Message Valid X Register

will be set.

Figure 26-47. Message Valid X Register (DCAN MSGVAL X) [offset = C0h]

31 16

Reserved

R-0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MsgValReg8 MsgValReg7 MsgValReg6 MsgValReg5 MsgValReg4 MsgValReg3 MsgValReg2 MsgValReg1

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Example 3

Bit 0 of the Message Valid X Register represents byte 0 of the Message Valid 1 Register. If one or more

bits in this byte are set, bit 0 of the Message Valid X Register will be set.

1201

SPNU562–May 2014 Controller Area Network (DCAN) Module

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