Datasheet

www.ti.com DCAN Control Registers
26.17.10 ECC Control and Status Register (DCAN ECC CS)
Figure 26-29. ECC Control and Status Register (DCAN ECC CS) [offset = 2Ch]
31 28 27 24 23 20 19 16
Reserved SBE_EVT_EN Reserved ECCMODE
R-0 R/WP-5h R-0 R/WP-Ah
15 9 8 7 1 0
Reserved DEFLG Reserved SEFLG
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset; U = Undefined
Table 26-16. ECC Control and Status Register (DCAN ECC CS) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 These bits are always read as 0. Writes have no effect.
27-24 SBE_EVT_EN Enable/disable SECDED single bit error event (CAN_SERR signal).
5h SECDED single bit error event is disabled, single bit errors are not signaled with a high pulse
on DCAN_SERR signal.
All other values SECDED single bit error event is enabled, single bit errors are signaled with a high pulse on
DCAN_SERR signal.
23-20 Reserved 0 These bits are always read as 0. Writes have no effect.
19-16 ECCMODE Enable/disable SECDED single bit error correction
5h SECDED single bit error correction disabled
All other values SECDED single bit error correction enabled
15-9 Reserved 0 These bits are always read as 0. Writes have no effect.
8 DEFLG Double bit error flag
0
Read: No double bit error detected.
Write: The bit is unchanged.
1
Read: Double bit error detected.
Write: The bit is cleared to 0.
7-1 Reserved 0 These bits are always read as 0. Writes have no effect.
0 SEFLG Single bit error flag
0
Read: No single bit error detected.
Write: The bit is unchanged.
1
Read: Single bit error detected
Write: The bit is cleared to 0.
1193
SPNU562–May 2014 Controller Area Network (DCAN) Module
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