Datasheet

www.ti.com DCAN Control Registers
26.17.5 Interrupt Register (DCAN INT)
Figure 26-24. Interrupt Register (DCAN INT) [offset = 10h]
31 24 23 16
Reserved Int1ID
R-0 R-0
15 0
Int0ID
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26-11. Interrupt Register (DCAN INT) Field Descriptions
Bit Field Value Description
31-24 Reserved 0 These bits are always read as 0. Writes have no effect.
23-16 Int1ID Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)
0 No interrupt is pending
1h-80h Number of message object which caused the interrupt.
81h-FFh Unused
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
with the highest priority. The DCAN1INT interrupt line remains active until Int1ID reaches
value 0 (the cause of the interrupt is reset) or until IE1 is cleared.
A message interrupt is cleared by clearing the message object's IntPnd bit.
Among the message interrupts, the message object's interrupt priority decreases with
increasing message number.
15-0 Int0ID Interrupt Identifier (the number here indicates the source of the interrupt)
0 No interrupt is pending
1h-80h Number of message object which caused the interrupt.
81h-7FFFh Unused
8000h Error and Status Register value is not 7h.
8001h-FFFFh Unused
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
with the highest priority. The DCAN0INT interrupt line remains active until Int0ID reaches
value 0 (the cause of the interrupt is reset) or until IE0 is cleared.
The Status Interrupt has the highest priority. Among the message interrupts, the message
object's interrupt priority decreases with increasing message number.
1189
SPNU562–May 2014 Controller Area Network (DCAN) Module
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