Datasheet

Debug/Suspend Mode www.ti.com
26.16 Debug/Suspend Mode
The module supports the usage of an external debug unit by providing functions like pausing DCAN
activities and making Message RAM content accessible via VBUSP interface.
Before entering debug/suspend mode, the circuit will either wait until a started transmission or reception
will be finished and Bus idle state is recognized, or immediately interrupt a current transmission or
reception. This is depending on bit IDS in CAN Control Register.
Afterwards, the DCAN enters debug/suspend mode, indicated by InitDbg flag in CAN Control Register.
During Debug/Suspend mode, all DCAN registers can be accessed. Reading reserved bits will return 0;
writing to reserved bits will have no effect.
Also, the Message RAM will be memory mapped. This allows the external debug unit to read the Message
RAM. For the memory organization, see Section 26.5.3).
NOTE: During Debug/Suspend Mode, the Message RAM cannot be accessed via the IFx register
sets.
Writing to control registers in debug/suspend mode may influence the CAN state machine
and further message handling.
For debug support, the auto clear functionality of the following DCAN registers is disabled:
• Error and Status Register (clear of status flags by read)
• IF1/IF2 Command Registers (clear of DMAActive flag by read/write)
26.17 DCAN Control Registers
Table 26-6 lists the control registers of the DCAN. After hardware reset, the registers of the DCAN hold
the values shown in the register descriptions. The base address for the control registers is FFF7 DC00h
for DCAN1, FFF7 DE00h for DCAN2, FFF7 E000h for DCAN3, and FFF7 E200h for DCAN4.
Additionally, the Bus-Off state is reset and the CAN_TX pin is set to recessive (HIGH). The Init bit in the
CAN Control Register is set to enable the software initialization. The DCAN will not influence the CAN bus
until the CPU resets Init to 0.
Table 26-6. DCAN Control Registers
Offset Acronym Register Description Section
00h DCAN CTL CAN Control Register Section 26.17.1
04h DCAN ES Error and Status Register Section 26.17.2
08h DCAN ERRC Error Counter Register Section 26.17.3
0Ch DCAN BTR Bit Timing Register Section 26.17.4
10h DCAN INT Interrupt Register Section 26.17.5
14h DCAN TEST Test Register Section 26.17.6
1Ch DCAN PERR Parity Error Code Register Section 26.17.7
24h DCAN ECCDIAG ECC Diagnostic Register Section 26.17.8
28h DCAN ECCDIAG STAT ECC Diagnostic Status Register Section 26.17.9
2Ch DCAN ECC CS ECC Control and Status Register Section 26.17.10
30h DCAN ECC SERR ECC Single Bit Error Code Register Section 26.17.11
80h DCAN ABOTR Auto-Bus-On Time Register Section 26.17.12
84h DCAN TXRQX Transmission Request X Register Section 26.17.13
88h DCAN TXRQ12 Transmission Request 12 Register Section 26.17.14
8Ch DCAN TXRQ34 Transmission Request 34 Register Section 26.17.14
90h DCAN TXRQ56 Transmission Request 56 Register Section 26.17.14
94h DCAN TXRQ78 Transmission Request 78 Register Section 26.17.14
98h DCAN NWDATX New Data X Register Section 26.17.15
1180
Controller Area Network (DCAN) Module SPNU562–May 2014
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