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26.15 SECDED Mechanism
The DCAN module provides a single error correction and double error detection (SECDED) mechanism to
ensure data integrity of Message RAM data. For each message object (136 bits) in the Message RAM, 9
ECC bits will be calculated. See Section 26.5.5.
The ECC bits are stored in a dedicated RAM. They will be generated on write accesses and will be
checked on read accesses.
The SECDED functionality can be enabled or disabled by PMD bit field in CAN Control Register. If
SECDED is enabled, ECC bits will be automatically generated and checked.
With the ECCMODE field in the ECC Control and Status register the single bit error correction can be
enabled or disabled (default: enabled).
NOTE: During RAM initialization, no ECC check will be done, but if the PMD bit is set, the ECC bits
will be generated.
26.15.1 Behavior on Single Bit Error
If a single bit error is detected with single bit error correction enabled, the correction will be done and the
SEFLG in the ECC Control and Status register will be set.
If single bit error correction is disabled and a single bit error is detected then the SEFLG in the ECC
Control and Status register and the the PER bit in the Error and Status register will be set. If error
interrupts are enabled, also an interrupt would be generated. In order to avoid the transmission of invalid
data over the CAN bus, the MsgVal bit of the message object will be reset.
The message object number where the single bit error has occurred will be indicated in the ECC Single Bit
Error Code Register.
When single bit error correction is disabled the message object data can be read by the host CPU,
independently of single bit errors. Thus, the application has to ensure that the read data is valid, for
example, by immediately checking the ECC Single Bit Error Code Register on single bit error interrupt.
26.15.2 Behavior on Double Bit Error
If a double bit error is detected, then the DEFLG in the ECC Control and Status register and the PER bit in
Error and Status Register will be set. If error interrupts are enabled, also an interrupt would be generated.
In order to avoid the transmission of invalid data over the CAN bus, the MsgVal bit of the message object
will be reset. The message object number will be indicated in the Parity Error Code Register.
The message object data can be read by the host CPU, independently of double bit errors. Thus, the
application has to ensure that the read data is valid, for example, by immediately checking the Parity Error
Code register on double bit error interrupt.
26.15.3 SECDED Testing
Testing of the SECDED mechanism can be implemented by using the diagnostic mode, which is enabled
with the ECCDIAG register. The following procedure can be used:
1. Disable SECDED using DCAN control register. Enable diagnostic mode using the ECCDIAG register
2. Write to corrupt the data (in RDA mode) or ECC bits.
3. Enable SECDED and read data for which ECC is corrupted (either in RDA mode or via IFx registers).
4. Single bit error or double bit error flag will be set in the diagnostic status register (ECCDIAG STAT) and
in the ECC Control and Status register accordingly. A double bit error or a single bit error with single bit
error correction disabled also triggers the PER flag.
5. Disable diagnostic mode.
1179
SPNU562–May 2014 Controller Area Network (DCAN) Module
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