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Message Interface Register Sets

26.6 Message Interface Register Sets

Accesses to the Message RAM are performed via the Interface Register sets:

• Interface Register 1 and 2 (IF1 and IF2)

• Interface Register 3 (IF3)

The IF3 register set can be configured to automatically receive control and user data from the Message

RAM when a message object has been updated after reception of a CAN message. The CPU does not

need to initiate the transfer from Message RAM to IF3 register set.

The Message Handler avoids potential conflicts between concurrent accesses to Message RAM and CAN

frame reception/transmission.

There are two modes where the Message RAM can be directly accessed by the CPU:

1. In Debug/Suspend mode (see Section 26.5.3)

2. In RAM Direct Access (RDA) mode (see Section 26.5.4)

For the Message RAM Base address, refer to the device datasheet.

A complete message object (see Section 26.5.1) or parts of the message object may be transferred

between the Message RAM and the IF1/IF2 Register set (see Section 26.17.23) in one single transfer.

26.6.1 Message Interface Register Sets 1 and 2

The Interface Register sets IF1 and IF2 provide indirect read/write access from the CPU to the Message

RAM. The IF1 and IF2 register sets can buffer control and user data to be transferred to and from the

message objects.

Table 26-4. Message Interface Register Sets 1 and 2

Address IF1 Register Set Address IF2 Register Set

[CAN Base +] 31 16 15 0 [CAN Base +] 31 16 15 0

IF1 Command IF2 Command

0x100 IF1 Command Mask 0x120 IF2 Command Mask

Request Request

0x104 IF1 Mask 2 IF1 Mask 1 0x124 IF2 Mask 2 IF2 Mask 1

0x108 IF1 Arbitration 2 IF1 Arbitration 1 0x128 IF2 Arbitration 2 IF2 Arbitration 1

0x10C Rsvd IF1 Message Control 0x12C Rsvd IF2 Message Control

0x110 IF1 Data A 2 IF1 Data A 1 0x130 IF2 Data A 2 IF2 Data A 1

0x114 IF1 Data B 2 IF1 Data B 1 0x134 IF2 Data B 2 IF2 Data B 1

1159

SPNU562–May 2014 Controller Area Network (DCAN) Module

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