Datasheet
3µs
2x(13x(9µs - 3µs))
-----------------------------------------------------------
min(TSeg1, TSeg2)
2x(13x(bit_time - TSeg2))
-----------------------------------------------------------------------
www.ti.com
CAN Module Configuration
26.3.2.4 Example for Bit Timing at Low Baudrate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
t
q
100 ns = 2 • t
CAN_CLK
delay of bus driver 200 ns
delay of receiver circuit 80 ns
delay of bus line (40m) 220 ns
t
Prop
1 µs = 1 • t
q
t
SJW
4 µs = 4 • t
q
t
TSeg1
5 µs = t
Prop
+ t
SJW
t
TSeg2
3 µs = Information Processing Time + 3 • t
q
t
Sync-Seg
1 µs = 1 • t
q
bit time 9 µs = t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for CAN_CLK 0.43 % =
(38)
=
(39)
In this example, the concatenated bit time parameters are (3-1)
3
&(5-1)
4
&(4-1)
2
&(2-1)
6
, so the Bit Timing
Register is programmed to 0000 24C1h.
26.4 CAN Module Configuration
After a hardware reset all CAN protocol functions are disabled.The CAN module must be initialized and
configured before it can participate on the CAN bus.
26.4.1 DCAN RAM Initialization Through Hardware
To start with a clean DCAN RAM ,the complete DCAN RAM has to be initialized with zeros and the ECC
bits set accordingly by configuring the following registers in the system module:
1. Memory Hardware Initialization Global Control Register (MINITGCR)
2. Memory Initialization Enable Register (MSINENA)
For more details on RAM hardware initialization support, refer to the system module reference guide.
26.4.2 CAN Module Initialization
To initialize the CAN Controller, you have to set up the CAN Bit timing and those message objects that
have to be used for CAN communication. Message objects that are not needed, can be deactivated.
So the two critical steps are:
1. Configuration of CAN Bit Timings
2. Configuration of Message Objects
26.4.2.1 Software Configuration of CAN Bit Timings
This step involves configuring the CAN baud rate register with the calculated CAN bit timing value. The
calculation procedure of CAN bit timing values for BTR register are mentioned in Section 26.3. Refer to
Figure 26-3 for CAN bit timing software configuration flow.
1151
SPNU562–May 2014 Controller Area Network (DCAN) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated