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25.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)
The GIOENASET and GIOENACLR registers control which interrupt-capable pins are actually configured
as interrupts. If the interrupt is enabled, the rising or falling or both edges on the selected pin lead to an
interrupt.
25.5.4.1 GIOENASET Register
Figure 25-8 and Table 25-5 describe this register.
NOTE: Enabling Interrupt at the Device Level
GIO can be mapped to two different device level interrupts, the GIO high-level (level A) and
low-level (level B) interrupts through programming registers GIOLVLSET and GIOLVLCLR.
The corresponding bit to the mapped device level interrupt must be set within the vectored
interrupt manager (VIM) in the interrupt mask register (REQMASK) to enable the appropriate
interrupts. Additionally, the ARM CPU (CPSR bit 7 or 6) must be cleared to recognize
interrupt requests (IRQ/FIQ).
Figure 25-8. GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h]
31 24 23 16
GIOENASET 3 GIOENASET 2
R/W-0 R/W-0
15 8 7 0
GIOENASET 1 GIOENASET 0
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-5. GIO Interrupt Enable Set Register (GIOENASET) Field Descriptions
Bit Field Value Description
31-24 GIOENASET 3 Interrupt enable for pins GIOD[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Enables the interrupt.
23-16 GIOENASET 2 Interrupt enable for pins GIOC[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Enables the interrupt.
15-8 GIOENASET 1 Interrupt enable for pins GIOB[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Enables the interrupt.
7-0 GIOENASET 0 Interrupt enable for pins GIOA[7:0]
0 Read: The interrupt is disabled.
Write: Writing a 0 to this bit has no effect.
1 Read: The interrupt is enabled.
Write: Enables the interrupt.
1128
General-Purpose Input/Output (GIO) Module SPNU562–May 2014
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