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24.6 Examples
24.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP
Table 24-50. Application Examples for Setting the Transfer Modes of CP A and B of a DCP
CP A CP B
Buffer A can be used as a "one shot" buffer. A buffer full interrupt enabled for CP A
One shot Not used
can signal reaching the end of the buffer.
Can double the buffer size for a "one shot" buffer. A buffer full interrupt enabled for CP
Auto switch One shot
B can signal reaching the end of the buffer.
The CPU can switch the buffers at arbitrary times. It will fill or read the frozen buffer
Circular Circular during the other buffer is filled or read by the HTU. Interrupts are not required for this
case.
Buffer full interrupts (enabled for CP A and B) signal when the end of a buffer is
reached. After one buffer is completed the according CPU interrupt routine will read or
Auto switch Auto switch refill this buffer. At the same time the other buffer is read or filled by the HTU. Here the
time when the buffer must be read is determined by the time of the interrupt
(determined by the frequency of the NHET transfer requests).
24.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B
The example assumes the NHET address to be read and the main memory address to be written.
I1 CPU initializes initial DCP: IFADDRA, IFADDRB, IHADDRCT, ITCOUNT
I2 CPU clears current DCP: CFADDRA, CFADDRB, CFTCTA, CFTCTB
I3 CPU clears BFINTFL flag of CP A and B
I4 Enable CP A with the CPENA register. Now the HTU fills buffer A
After some time the CPU intends to read buffer A:
CPU enables CP B and disables CP A by writing to the CPENA register. After this
A1 switch, the HTU fills buffer B. Filling buffer B starts with its initial full address and initial
frame counter
A2 CPU waits for CP A busy bit equals zero
Optional: CPU verifies that the CP A request lost flag is not set. The bus error flag of CP
A3
A could also be checked
A4 CPU reads the frozen CFTCTA, which indicates the fill level in the buffer
CPU sets current CP A (CFTCTA and/or CFADDRA) to zero. This allows to find out if
A5
any request has happened during the next time buffer A is active
A6 CPU reads BFINTFL flag of buffer A
CPU clears the BFINTFL flag of buffer A. This is an initialization for the next time buffer
A7
A is used
CPU reads valid values of frozen buffer A. After reading the CPU does not need to clear
A8
the frozen buffer A
1115
SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module
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