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Double Control Packet Configuration Memory

Table 24-45. Initial NHET Address and Control Register (HTU IHADDRCT) Field Descriptions (continued)

Bit Field Value Description

15-13 Reserved 0 Read returns 0. Writes have no effect.

12-2 IHADDR Initial NHET Address

The initial NHET Address points to the NHET field, which is the first element of the frame. The

NHET address (Bits 12:2) increments by one for each 32-bit NHET field and starts with zero at the

first 32-bit field in the NHET RAM.

Note: When the HTU addresses the NHET RAM it uses only the number of address bits required

for the actual NHET RAM size. If the NHET address exceeds the actual NHET RAM size, the

unused MSB bits of the address will be ignored and the address rolls over to the start of the NHET

RAM.

1-0 Reserved 0 Read returns 0. Writes have no effect.

24.5.4 Initial Transfer Count Register (HTU ITCOUNT)

Figure 24-45. Initial Transfer Count Register (HTU ITCOUNT)

31 21 20 16

Reserved IETCOUNT

R-0 R/WP-X

15 8 7 0

Reserved IFTCOUNT

R-0 R/WP-X

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown

Table 24-46. Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions

Bit Field Value Description

31-21 Reserved 0 Read returns 0. Writes have no effect.

20-16 IETCOUNT Initial Element Transfer Count

Defines the number of element transfers.

15-8 Reserved 0 Read returns 0. Writes have no effect.

7-0 IFTCOUNT Initial Frame Transfer Count

Defines the number of frame transfers.

1111

SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module

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