Datasheet

www.ti.com HTU Control Registers
Table 24-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions (continued)
Bit Field Value Description
15-12 Reserved 0 Read returns 0. Writes have no effect.
11-8 CPNUM1 Control Packet Number for single memory protection region configuration. CPNUM1 holds the
number of the CP, which has caused the first memory protection error when only one memory
protection region is used. This number is not updated for multiple access violations until it is read
by the CPU. During debug mode, CPNUM1 is frozen even when read.
0 CP A of DCP0
1h CP B of DCP0
2h CP A of DCP1
3h CP B of DCP1
4h CP A of DCP2
5h CP B of DCP2
6h CP A of DCP3
7h CP B of DCP3
8h CP A of DCP4
9h CP B of DCP4
Ah CP A of DCP5
Bh CP B of DCP5
Ch CP A of DCP6
Dh CP B of DCP6
Eh CP A of DCP7
Fh CP B of DCP7
7-6 Reserved 0 Read returns 0. Writes have no effect.
5 INTENA01 Interrupt Enable 01. This bit needs to be set when working with two memory mapped regions and
a error should be generated to the ESM module on an access violation.
0 Error signaling is disabled
1 Error signaling is enabled
4 ACCR01 Access Rights 01. This bit defines the access rights for the HTU for accesses outside the region
defined by the MP0S and MP0E and the MP1S and MP0E registers.
0 HTU read access is allowed but write access will be signaled
1 Any access performed by the HTU is forbidden and will be signaled
3 REG01ENA Region Enable 01. This bit needs to be set when working with two memory mapped regions.
REG0ENA must be set to zero if this bit is set to a one. Memory region 0 must be less than
memory region 1.
0 The protection outside the memory region defined by the MP0S and MP0E and the MP1S and
MP0E registers is not enabled. This means the HTU can access any implemented memory space.
REG0ENA could still enabled to give protection outside the MP0S : MP0E region.
1 The protection outside the memory region defined by the MP0S and MP0E and the MP1S and
MP0E registers is enabled. This means the HTU can perform any access within the regions, but if
it attempts to perform a forbidden access outside of both of the regions (according to the ACCR01
configuration), the access is signaled by the MPEFT1 flag. The number of the CP, which has
caused the memory protection error, is captured to CPNUM1 if it is not currently frozen and an
error is generated if it is enabled.
2 INTENA0 Interrupt Enable 0. This bit needs to be set when working with one memory mapped region and a
error should be generated to the ESM module on an access violation.
0 Error signaling is disabled
1 Error signaling is enabled
1 ACCR Access Rights 0. This bit defines the access rights for the HTU for accesses outside the region
defined by the MP0S and MP0E registers for a single memory protection region configuration.
0 HTU read access is allowed but write access will be signaled
1 Any access performed by the HTU is forbidden and will be signaled
1105
SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module
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