Datasheet
HTU Control Registers
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24.4.26 Memory Protection Control and Status Register (HTU MPCS)
Figure 24-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]
31 28 27 24
Reserved CPNUM0
R-0 R-0
23 18 17 16
Reserved MPEFT1 MPEFT0
R-0 R/WCP-0 R/WCP-0
15 12 11 8
Reserved CPNUM1
R-0 R-0
7 6 5 4 3 2 1 0
Reserved INT ENA01 ACCR01 REG01ENA INT ENA0 ACCR0 REG0ENA
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; WPC = Write 1 in privilege mode to clear the bit; -n =
value after reset
Table 24-39. Memory Protection Control and Status Register (HTU MPCS) Field Descriptions
Bit Field Value Description
31-28 Reserved 0 Read returns 0. Writes have no effect.
27-24 CPNUM0 Control Packet Number for single memory protection region configuration. CPNUM0 holds the
number of the CP, which has caused the first memory protection error when only one memory
protection region is used. This number is not updated for multiple access violations until it is read
by the CPU. During debug mode, CPNUM0 is frozen even when read.
0 CP A of DCP0
1h CP B of DCP0
2h CP A of DCP1
3h CP B of DCP1
4h CP A of DCP2
5h CP B of DCP2
6h CP A of DCP3
7h CP B of DCP3
8h CP A of DCP4
9h CP B of DCP4
Ah CP A of DCP5
Bh CP B of DCP5
Ch CP A of DCP6
Dh CP B of DCP6
Eh CP A of DCP7
Fh CP B of DCP7
23-18 Reserved 0 Read returns 0. Writes have no effect.
17 MPEFT1 Memory Protection Error Fault Flag 1. This bit is set, when the HTU performs an access outside
the region defined by the MP0S and MP0E and the MP1S and MP0E registers, when the access
violates the rights defined by ACCR01 and when the REG01ENA bit is set.
0 No fault detected. Writing a zero has no effect.
1 Fault detected. Writing a one will clear the bit.
16 MPEFT0 Memory Protection Error Fault Flag 0. This bit is set, when the HTU performs an access outside
the region defined by the MP0S and MP0E registers, when the access violates the rights defined
by ACCR and when the REG0ENA bit is set.
0 No fault detected. Writing a zero has no effect.
1 Fault detected. Writing a one will clear the bit.
1104
High-End Timer Transfer Unit (HTU) Module SPNU562–May 2014
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