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HTU Control Registers

24.4.25 Parity Address Register (HTU PAR)

Figure 24-38. Parity Address Register (HTU PAR) [offset = 68h]

31 17 16

Reserved PEFT

R-0 R/WPC-0

15 9 8 0

Reserved PAOFF

R-0 R-X

LEGEND: R/W = Read/Write; R = Read only; WPC = Write 1 in privilege mode to clear the bit; -n = value after reset; X = undefined

Table 24-38. Parity Address Register (HTU PAR) Field Descriptions

Bit Field Value Description

31-10 Reserved 0 Read returns 0. Writes have no effect.

16 PEFT Parity Error Fault Flag. This bit is set, when the HTU detects a parity error and parity checking is

enabled.

0 No fault detected

1 Fault detected

Note: Once PEFT is set, a read access to the lower 16 bits or to the complete 32-bit HTUPAR

1 to the PEFT bit.

15-9 Reserved 0 Read returns 0. Writes have no effect.

8-0 PAOFF Parity Error Address Offset. This bit field holds the address of the first parity error, which is

detected in the DCP RAM. PAOFF provides the offset address of the erroneous byte counted from

the beginning of the DCP memory. This error address is frozen from being updated until a read

access to the lower 16 bits or to the complete 32-bit HTUPAR register happens. During debug

mode, this address is frozen even when read.

Note: The Parity Error Address bits will not be reset, neither by PORRST nor by any other reset

source.

1103

SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module

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