Datasheet

HTU Control Registers www.ti.com
24.4.24 Parity Control Register (HTU PCR)
Figure 24-37. Parity Control Register (HTU PCR) [offset = 64h]
31 17 16
Reserved COPE
R-0 R/WP-0
15 9 8 7 4 3 0
Reserved TEST Reserved PARITY_ENA
R-0 R/WP-0 R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 24-37. Parity Control Register (HTU PCR) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Read returns 0. Writes have no effect.
16 COPE Continue on Parity Error
0 The HTU performs parity checks every time it reads the RAM section of DCP x (with x = 0, 1,...
or 7), before the next frame (of DCP x) is started. If a parity error is detected during this read
access and if the parity check is enabled, then the frame will not be started and DCP x will be
automatically disabled in the CPENA register.
If a master different than the HTU (for example, CPU) reads the RAM section of DCP x and a
parity error is detected during this read access, while the parity check is enabled, then the DCP
x will automatically be disabled in the CPENA register. If a frame is active on DCP x during this
read access, then in addition the element counter of DCP x is cleared and all new element
transfers on DCP x are stopped and the active busy bit of DCP x is cleared.
1 The difference to COPE=0 is, that the data transfer on a active DCP continues after a parity
error was detected on this DCP. So neither the DCP with the parity error will be disabled nor
the frame will be stopped.
15-9 Reserved 0 Read returns 0. Writes have no effect.
8 TEST Test. When this bit is set, the parity bits are mapped into the peripheral RAM frame to make
them accessible by the CPU.
0 Parity bits are not memory mapped
1 Parity bits are memory mapped
7-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 PARITY_ENA Enable/Disable Parity Checking. This bit field enables or disables the parity check on read
operations and the parity calculation on write operations. If parity checking is enabled and a
parity error is detected, then the PEFT flag is set, PAOFF is captured if it is not currently frozen
and an interrupt is generated if it is enabled.
5h Parity check is disabled
All Others Parity check is enabled
Note: It is recommended to write Ah to enable error detection, to guard against single bit
changes from flipping PARITY_ENA to a disable state.
1102
High-End Timer Transfer Unit (HTU) Module SPNU562–May 2014
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