Datasheet
132
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of
the CPU.
6.20 Reset / Abort / Error Sources
Table 6-46. Reset/Abort/Error Sources
ERROR SOURCE SYSTEM MODE ERROR RESPONSE
ESM HOOKUP
GROUP.CHANNE
L
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) N/A
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) N/A
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) N/A
Illegal instruction User/Privilege
Undefined Instruction Trap
(CPU)
(1)
N/A
MPU access violation User/Privilege Abort (CPU) N/A
Correctable error User/Privilege ESM 1.4
Uncorrectable error User/Privilege ESM => NMI 2.21
LEVEL 2 SRAM
CPU Write ECC single error (correctable) User/Privilege ESM 1.26
ECC double bit error:
Read-Modify-Write (RMW) ECC double error
CPU Write ECC double error
User/Privilege Bus Error, ESM => nERROR 3.3
Uncorrectable error Type A:
Write SECDED malfunction error
Redundant address decode error
Read SECDED malfunction error
User/Privilege Bus Error, ESM => nERROR 3.14
Uncorrectable error type B:
Memory scrubbing SECDED malfunction error
Memory scrubbing Redundant address decode error
Memory scrubbing address/control parity error
Write data merged mux diagnostic error
Write SECDED malfunction diagnostic error
Read SECDED malfunction diagnostic error
Write ECC correctable and uncorrectable diagnostic error
Read ECC correctable and uncorrectable diagnostic error
Write data merged mux error
Redundant address decode diagnostic error
Command parity error on idle
User/Privilege ESM => NMI 2.7
Address/Control parity error User/Privilege Bus Error, ESM => nERROR 3.15
Level 2 RAM illegal address error Memory initialization error User/Privilege Bus Error N/A
FLASH
L2FMC correctable error - single bit ECC error for implicit OTP
read
User/Privilege ESM 1.6
L2FMC uncorrectable error - double bit ECC error for implicit
OTP read
User/Privilege ESM => NMI 2.19
L2FMC fatal uncorrectable error:
address parity error/internal parity error
address tag error
Internal switch time-out
User/Privilege Bus Error, ESM => nERROR 3.13
L2FMC parity error:
Mcmd parity error on Idle command
POM idle state parity error
Port A/B Idle state parity error
User/Privilege ESM => NMI 2.17
L2FMC nonfatal uncorrectable error:
Response error on POM
Response parity error on POM
Bank accesses during special operation (program/erase) by the
FSM
Bank/Pump in sleep
Unimplemented special/unavailable space
User/Privilege Bus Error N/A