Datasheet

HTU Control Registers www.ti.com
Table 24-19. Active Control Packet and Error Register (HTU ACPE) Field Descriptions (continued)
Bit Field Value Description
28-24 ERRETC Error Element Transfer Count
If one of the following conditions happens the current element transfer counter of the control packet
(specified by ERRCPN) is captured to ERRETC. Please see also Conditions for Frame Transfer
Interruption.
• Request Lost Error of control packet specified by ERRCPN. This is independent of the CORL bit.
• Parity Error of control packet specified by ERRCPN. This requires the parity check to be enabled, but
is independent of the COPE bit.
• Bus Error of control packet specified by ERRCPN.
• Memory Protection Error of control packet specified by ERRCPN. This requires the memory
protection to be enabled.
• Writing a one to a BUSY bit, which belongs to the control packet specified by ERRCPN, if that bit is
one. There is no effect if the BUSY bit is zero.
ERRETC is frozen from being updated until the upper 16-bit word of the ACPE register or the complete
32-bit register is read by the CPU. After this read the HTU will update ERRETC if one of the above
conditions is fulfilled again. During debugging, ERRETC stays frozen even when reading the upper 16-
bit word or the 32-bit register.
23-20 Reserved 0 Read returns 0. Writes have no effect.
19-16 ERRCPN Error Control Packet Number
If one of the conditions listed at ERRETC happens the number of the control packet, which caused the
condition, is captured to ERRCPN.
Control Packet ERRCPN Value
CP A of DCP x 2 x
CP B of DCP x 2 x+1
With x = 0,1,...or 7
ERRCPN is frozen from being updated until the upper 16-bit word of the ACPE register or the complete
32-bit register is read by the CPU. After this read the HTU will update ERRCPN if one of the above
conditions is fulfilled again. During debugging, ERRCPN stays frozen even when reading the upper 16-
bit word or the 32-bit register. If one of the conditions is fulfilled ERRETC and ERRCPN are updated
simultaneously.
15 TIPF Transfer in Progress Flag
0 No transfers are in progress
1 A transfer is currently active. This bit is the result of a logical OR function of all BUSYxx flags of the 4
BUSYx registers.
14 BUSBUSY Bus is Busy
0 Bus between NHET and HTU is not busy
1 When BUSBUSY is one the bus is busy with a transfer. It is different from TIPF above because
BUSBUSY will go low after VBUSHOLD is set to one and no transfers are pending between the HTU
and the main memory. TIPF will remain one if a transfer is still pending and VBUSPHOLD is one.
13 Reserved 0 Read returns 0. Writes have no effect.
12-8 CETCOUNT Current Element Transfer Count
CETCOUNT shows the current element transfer counter for the frame which is currently processed. If
the HTU doesn't currently transfer any frame CETCOUNT is zero.
CETCOUNT is updated after the write part of a transfer. There is a period of up to 7 cycles between the
time the CETCOUNT is zero and the HTU is finished updating the current DCP (and the CPENA
registers if the required conditions are fulfilled).
7-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 NACP Number of Active Control Packet
Indicates which CP currently processes a frame.
Active or Recent DCP NACP Value
CP A of DCP x 2 x
CP B of DCP x 2 x+1
With x = 0,1,...or 7
NACP is updated at the time the frame starts on the according CP, and it is updated with a new value
when a frame starts on a different CP. Note, that there can be a delay between the request and the start
of the frame.
1088
High-End Timer Transfer Unit (HTU) Module SPNU562–May 2014
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