Datasheet

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24.4.1 Global Control Register (HTU GC)
Figure 24-14. Global Control Register (HTU GC) [offset = 00]
31 25 24 23 17 16
Reserved VBUSHOLD Reserved HTUEN
R-0 R/WP-0 R-0 R/WP-0
15 9 8 7 1 0
Reserved DEBM Reserved HTURES
R-0 R/WP-0 R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 24-11. Global Control Register (HTU GC) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Read returns 0. Writes have no effect.
24 VBUSHOLD Hold the VBUS bus
0 The VBUS is not held
1 The VBUSHOLD bit holds the bus used to transfer data between the HTU and the NHET module.
When the BUS_BUSY bit is zero then the bus is no longer busy. While the bus is held, requests
will still be accepted. They will be acted upon when the VBUSHOLD is zero. Request lost
conditions will be detected and interrupts generated if they are enabled.
23-17 Reserved 0 Read returns 0. Writes have no effect.
16 HTUEN Transfer Unit Enable Bit
0 The Transfer Unit is disabled
1 The Transfer Unit is enabled
The configuration registers and control packets should be set up first before the HTUEN bit is set
to 1 to prevent it from carrying out unintended bus transactions. If the HTUEN bit is cleared to 0
during a frame is transferred, then the frame will be completed before the HTU is disabled.
The HTUEN bit must be cleared to 0 and the parity functionality must be enabled (by
PARITY_ENA) during the automatic DCP RAM initialization (see Initializing Parity Bits). If HTUEN
is one when the initialization is triggered by the system module, then the initialization will not be
performed and the HTU operation is not affected. If a 1 is written to HTUEN during the
initialization, then the HTUEN bit will be set but the HTU will not be enabled before the initialization
completes.
Note: If HTU is disabled during a frame transfer, then the ongoing current frame will be
completed before the HTU module is disabled. If enabled again, then the transfer will restart
from the initial frame count for the CP programmed.
15-9 Reserved 0 Read returns 0. Writes have no effect.
8 DEBM Debug Mode
0 The Transfer Unit is stopped in debug mode.
The HTU will complete the current frame, but not start any new frames. It will also ignore all
requests from the HET and not generate any request lost signals.
1 The Transfer Unit continues operation in debug mode
Note: Since the HET has also an " ignore suspend" bit, there a several possibilities for the behavior
of the HET and HTU in suspend mode.
7-1 Reserved 0 Read returns 0. Writes have no effect.
0 HTURES HTU Software Reset Request
0 Reset request is not issued to the HTU module. Writing a zero has no effect.
1 Reset request is issued to the HTU module.
Ongoing element transfers will be completed, before resetting the complete HTU module, similar to
a hardware reset. The HTURES bit will also be cleared. The recommended order of operations is:
• Set the software reset bit. This also clears HTUEN.
• Wait for the HTURES bit to clear.
• Configure the HTU registers and packets.
• Set the HTUEN bit to begin operation.
1083
SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module
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