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Module Operation

If an element transfer of DCP x generates a memory protection error, then:

1. The element counter of DCP x is cleared.

2. All new element transfers on DCP x are stopped.

3. The active busy bit of DCP x is cleared.

4. DCP x is disabled in the CPENA register. The DCPs other than DCP x will not be affected.

5. The FT flag will be set.

6. An error is signaled to the ESM module.

24.2.6 Control Packet RAM Parity Checking

The HTU module can detect parity errors in the DCP (Double Control Packet) RAM. DCP RAM parity

checking is implemented using one parity bit per byte. Even or odd parity checking can be selected in the

DEVCR1 register of the system module and can be enabled/disabled by a 4-bit key in the PCR register.

During a read access to the DCP RAM, the parity is calculated based on the data read from the RAM and

compared with the good parity value stored in the parity bits. The parity check is performed when the HTU

or any other master (for example, CPU) makes a read access to the DCP RAM. A read access within the

RAM section of an initial or current DCP checks all 16 bytes of the DCP at a time (see also DCP memory

map). For example, if a byte read access happens for DCP RAM address 0, but there is a parity error at

byte address Ch then the parity error will occur and the captured parity address will be Ch and not 0. The

address of the byte in which the error occurred can be read from the PAR register. If successive DCP

RAM read accesses generate multiple parity errors, only the address of the first detected error will be

captured and the PAR register will not be updated by subsequent errors until it is read by the application.

When multiple errors in a 16 byte word are detected, only the address of the lowest byte will be captured.

The application can decide whether to stop any transfers when a parity error is detected or to continue

transferring data. If the COPE (Continue On Parity Error) bit is zero and parity checking is enabled, then

the HTU will not start the frame and the corresponding DCP will be automatically disabled in the CPENA

error is detected during this read access, while the parity check is enabled and the COPE bit is zero, then

the DCP x will be automatically disabled in the CPENA register. If a frame for this DCP x is ongoing during

this read access, then in addition the element counter of DCP x is cleared, all new element transfers on

DCP x are stopped and the active busy bit of DCP x is cleared. With COPE set to one and the parity

check enabled, the parity checking will still be performed, but the data transfer of an active DCP continues

after a parity error was detected for this DCP. So neither the DCP with the parity error will be disabled nor

the frame will be stopped.

After a DCP is enabled (with CPENA using BIM=0), then at the start of the first frame, the HTU performs

the parity check only on the initial DCP, since it does not need the current DCP information. For further

frames, the HTU performs the parity check for both initial and current DCP, since it needs both

information.

On a parity error detection, an error will also be signaled to the ESM module.

1077

SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module

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