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1301

Pin CC6

L00-CNT-DF 20 21 22 23 24

L01-WCAP-DF 22

L02-WCAP-DF 21 24

LRP

OKRL

e1 e2

TU Delay Frame

r(n)

f(n)

f(n-1)

e1 e2

r(n+1)

Module Operation

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In the case of very light HTU load, but higher signal requirements (for example, high frequency), the quiet

request could also be used to define periods in which the data read by a control packet is safe. The

following HET code will capture counter time stamps to the L1-WCAP data field after rising edges (at pin

CC6) and to the L2-WCAP data field after falling edges (at pin CC6):

L0 CNT {reg=A, max=0x1FFFFFF}

L1 WCAP {reqnum=3, request=GENREQ, event=RISE, reg=A, pin=CC6}

L2 WCAP {reqnum=3, request=QUIET, event=FALL, reg=A, pin=CC7}

; HET HRSHARE feature configured to assign both WCAPs to pin CC6

Figure 24-12. Timing Example for Two WCAP Instructions

The HTU frame will have two elements: The first gives the time stamp of the rising edge r(n) and the

second gives the time stamp of the previous falling edge f(n-1). Using the code above, requests (R) and

the quiet requests (QR) will occur at the times shown in Figure 24-12, and a request lost will only be

signaled when the frame makes an access during the times marked with RL. So reading [22, 21] as frame

elements is correct. If the signal frequency would increase, then a wrong pair [22,24] could be read, but

this will be signaled by a request lost error since at least e2 falls into the RL period.

24.2.5 Memory Protection

This feature allows restricting accesses to certain areas in memory in order to protect critical application

data from unintentionally being manipulated by the HTU.

If the HTU memory protection feature is disabled, the full 4 GB address range can be accessed by the

HTU without exception. There are two memory regions which start and end addresses can be configured.

With the memory protection feature enabled, read and write accesses by the HTU inside the defined

regions are allowed. For accesses outside the regions, one of two modes is configurable:

• Any access performed by the HTU is forbidden and will be signaled to the ESM module. Write

accesses will be blocked.

• Read access is allowed but write access will be blocked and signaled to the ESM module.

To use one region only, REG01ENA must be zero. Bits ACCR01, INTENA01, and register settings of

MP1S, and MP1E will be ignored.

To use both regions, the rules below must be followed:

1. Memory mapped region 0 covers a lower memory area as Memory mapped region 1.

2. REG01ENA is a one and REG0ENA is a zero.

3. ACCR01 is set for the desired access type, ACCR0 is ignored.

4. INTENA01 is set for the desired action, INTENA0 is ignored.

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High-End Timer Transfer Unit (HTU) Module SPNU562–May 2014

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