Datasheet

Frame Start
DCP Disable
Request
Busy Bit
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There could be a case where the CPU wants to do main memory operations, but does not want the HTU
modifying the main memory. It could happen that a request was already active, but the frame transfer
hasn't started yet when the application disabled the control packets. The timing diagram in Figure 24-8
shows this scenario.
Figure 24-8. Timing for Disabling Control Packets
Since the request for the transfer was already received before the DCPx is disabled, the HTU will still start
the frame transfer. The application would poll the BUSYx bit during the time the DCPx was disabled and
before the frame was started and would read a non-busy information. It then would start the main memory
operations thinking all transfers have completed, however after some time the HTU will start the
outstanding frame transfer and corrupt the main memory.
To avoid this, the application can set the VBUSHOLD bit to disable all transactions between the HTU and
the main memory. It has to poll the BUSBUSY bit to ensure that no outstanding transactions on the bus
are pending. The HTU will still receive all transfer requests from the NHET, but it will not be able to
transfer any data to or from the main memory, while the VBUSHOLD bit is set.
24.2.2 Arbitration of HTU Elements and Frames
• Frames do not interrupt each other. If a request occurs on DCP x while another frame runs on DCP y
(and x ≠ y), then the current frame completes before the new frame starts.
• If two or more request lines are active, the request line with the lower number (specified in the request
number field of the corresponding NHET instruction) is serviced first.
24.2.3 Conditions for Frame Transfer Interruption
If a frame is currently transferred on DCP x and one of the events listed below happens, then the event
will (1.) clear the element counter of DCP x, (2.) stop new element transfers on DCP x (3.) clear the active
busy bit of DCP x and (4.) disable DCP x in the CPENA register. The DCPs other than DCP x will not be
affected.
• Request Lost Error of DCP x (with CORL bit set to zero).
• Parity Error of DCP x (with parity check enabled and COPE bit set to zero). See also Section 24.2.6.
• Bus Error of DCP x.
• Memory Protection Error of DCP x (with memory protection enabled). See also Section 24.2.5 .
• Writing a one to a BUSY bit (belonging to DCP x) if that bit is one. There is no effect if the BUSY bit is
zero.
• Writing a one to the HTURES bit.
When a memory protection error occurs, the access to the protected address is blocked. The frame is
stopped before the element, which caused the violation transfer, starts. All other errors will let the current
element transfer finish.
In case of the Request Lost and Bus Error, one more element transfer goes on the bus, before the frame
is actually stopped. Accordingly, the busy bit is cleared after the element, which follows the element that
caused the error.
In case of the Bus Error, the counter for the element, which follows the element that caused the error, is
captured to the ERRETC register field.
1073
SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module
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