Datasheet

element counter
request
2 1
buffer location
U
1Ch
28h
0
34h
U
busy bit
buffer location
U 2 1
U 4Ch 58h
busy bit
0
64h
auto
switch
auto
switch
3
2
1
10h
14h
18h
3
2
1
1Ch
20h
24h
3
2
1
28h
2Ch
30h
3
2
1
3
2
1
3
2
1
frame counter
CFTCTB
full address
CFADDRB
buffer full flag
BFINTFL
frame counter
CFTCTA
full address
CFADDRA
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
Module Operation www.ti.com
The examples of Figure 24-7 assumes IETCOUNT=3 (Initial Element Transfer Count), IFTCOUNT=3
(Initial Frame Transfer Count, SIZE=0 (Size of Transfer = 32-bit) and ADDFM=0 (Addressing Mode Main
Memory = Post Increment). So there are in total 9 32-bit values in buffer A and B. It also assumes
IFADDRB=10h and IFADDRA=40h. "U" means uninitialized.
Figure 24-7. Timing Example for Auto Switch Buffer Mode
24.2.1.4 General Control Packet Behavior
The action defined by the selected mode will be performed at the end of the last frame, which has the
frame counter value of 1. The one shot and auto switch mode will automatically update the CPENA
register at this time. Note, that for all three modes listed above, it is possible to switch to the other buffer
by writing to CPENA before the end of the current buffer is reached.
If a write access to CPENA happens while the last frame of DCP x (with frame counter = 1) is transferred
then the priority is defined by Table 24-1.
Table 24-1. CPENA / TMBx Priority Rules
Write access to CPENA bits (2*x+1) and (2*x) during the
Priority Rule
frame with frame counter = 1 (
(1)
)
Disable:
Disabling the DCP by the write to CPENA has priority, TMBx is
01 --> 00 or
ignored.
10 --> 00
Stay:
The write access to CPENA is ignored, TMBx has priority and
01 --> 01 or
defines the action.
10 --> 10
Switch:
Switching the DCP by the write to CPENA has priority, TMBx is
01 --> 10 or
ignored.
10 --> 01
(1)
See read table of CPENA register
1072
High-End Timer Transfer Unit (HTU) Module SPNU562–May 2014
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