Datasheet

Memory View for DCP-1A/B
Increasing Address
Buffer 1A
Increasing Address
Buffer 1A
Buffer 1B
Switch
t1
TU request (1) X X X X
Element Counter 1A 5 4 3 2 1 5 4 3 2 1
Element Counter 1B 5 4 3 2 1 5 4 3 2 1
Element Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TU request (2) X X X X
Element Counter 2A 5 4 3 2 1 5 4 3 2 1
Element Counter 2B 5 4 3 2 1 5 4 3 2 1
Element Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
t2 t3
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
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Figure 24-6. Dual Buffer Timing
Figure 24-6 shows a switch at time t1, where buffer 1A is frozen and data stream 1 is directed to buffer
1B, but only after the frame has been completed. It also shows the time (t2 or t3) where 2A is frozen and
data stream 2 is directed to buffer 2B. If the switch happens between the request and the start of the
frame (for example, time t3), then the frame is processed by the new control packet (although the old
control packet was active at the time of the request). The delays between the HTU requests and the start
of the element transfers result from the fact that the HTU can process only one transfer at a time.
Auto Switch Buffer Mode
If TMBA is set to auto switch mode, then the data stream will continue at the start of buffer B after all
elements of buffer A have been transferred. This means that in the CPENA register, CP A is disabled and
CP B is enabled automatically and buffer B uses its initial main memory address and initial frame counter
to start. The same principle is valid for TMBB and buffer B.
1071
SPNU562–May 2014 High-End Timer Transfer Unit (HTU) Module
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