Datasheet

frame counter
CFTCTx
element counter
request
2 1
buffer location
U
full address
CFADDRx
1Ch 28h
0 2 1
34h 1Ch 28h
U
busy bit
buffer full flag
BFINTFL
frame counter
CFTCTx
element counter
request
1
buffer location
full address
CFADDRx
busy bit
buffer full flag
BFINTFL
3
2
1
10h
14h
18h
3
2
1
1Ch
20h
24h
3
2
1
28h
2Ch
30h
3
2
1
10h
14h
18h
3
2
1
1Ch
20h
24h
3
2
1
28h
2Ch
30h
end of
buffer
end of
buffer
Module Operation www.ti.com
Figure 24-5. Timing Example for Circular Buffer Mode
24.2.1.3 Dual Buffer Implementation
The transfer unit provides double control packets (DCPs) supporting the use of two buffers per data
stream (per HTU request source). If one buffer should be read by the CPU or DMA, the data stream is
directed to the other buffer and the first buffer is frozen. Switching to the other buffer can be triggered with
a write access to the CPENA register or with the DCP configured to automatically switch to the other
buffer when the programmed number of frames has been transmitted. Freezing the buffer avoids this
buffer to be overwritten with new HET data while the CPU or DMA reads this buffer.
Figure 24-6 shows a timing example of two HET instructions 1 and 2, which are the request sources for
the HTU (and are controlled by DCP 1 and DCP 2). Each generated frame has 5 element transfers.
Request source 1 has two RAM buffers, controlled by two control packets 1A and 1B. Request source 2
has two RAM buffers, controlled by two control packets 2A and 2B.
1070
High-End Timer Transfer Unit (HTU) Module SPNU562–May 2014
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