Datasheet

IC2
bit 31
0
IC2
bit 31
0
IC1
IC2
bit 31
0
0
0
bit 31
IC2
IC1
bit 31
0
0
bit 31
0
IC2
S
bit 31
0
Instruction Set www.ti.com
Table 23-54. Destination Operand Choices (continued)
Destination
Stored Value Address dest rdest
Operand
IMM D[31:0] = result [31:0] current instruction address C[7] = 1, C[2:1] = 10 n/a
NONE n/a n/a C[7] = 0, C[2:1] = 11 C[4:3] = 00
REM D[31:0] = result [31:0] specified by remote[8:0] n/a C[4:3] = 01
REMP P[8:0] = result [8:0] specified by remote[8:0] n/a C[4:3] = 10
Table 23-55. Shift Encoding
Shift Type C[15:13] smode Operation Illustrated
(1)
No Shift Applied 0 0 0 n/a - no shift
ASR-Arithmetic Shift Right 0 0 1
LSL-Logical Shift Left 0 1 0
CSL-Carry Shift Left 0 1 1
LSR-Logical Shift Right 1 0 0
CSR-Carry Shift Right 1 0 1
RR - Rotate Right 1 1 0
CRR – Carry Rotate Right 1 1 1
(1)
IC1 is the carry flag after the arithmetic / logical operation is performed. Ic2 is the updated carry flag after the shift operation is
performed. s is the sign bit.
Table 23-56. Execution Time for ADC, ADD, AND, OR, SBB, SUB, XOR Instructions
Cycle
src1 dest rdest remote[8:0]
s
ZERO, IMM, A, B, R, S, T, or ONES A,B,R,S,T, or NONE NONE ! = next[8:0] 1
REM or REMP A,B,R,S,T, or NONE NONE != next[8:0] 2
ZERO, IMM, A, B, R, S, T, or ONES IMM REM != next[8:0] 2
ZERO, IMM, A, B, R, S, T, or ONES A,B,R,S,T, or NONE REMP != next[8:0] 2
ZERO, IMM, A, B, R, S, T, or ONES A,B,R,S,T, or NONE NONE == next[8:0] 2
REM or REMP IMM REM x 3
x IMM REMP x 3
REM or REMP x REM == next[8:0] 3
x x REMP == next[8:0] 3
1008
High-End Timer (N2HET) Module SPNU562–May 2014
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