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23.5 Instruction Set
23.5.1 Instruction Summary
Table 23-49 presents a list of the instructions in the N2HET instruction set. The pages following describe
each instruction in detail.
Table 23-49. Instruction Summary
Abbreviation Instruction Name Opcode Sub-Opcode Cycles
(1)
ACMP Angle Compare Ch - 1
ACNT Angle Count 9h - 2
ADCNST Add Constant 5h - 2
ADC Add with Carry and Shift 4h C[25:23]=001, C5 = 1 1 - 3
ADD Add and Shift 4h C[25:23]=011, C5 = 1 1 - 3
ADM32 Add Move 32 4h C[25:23]=000, C5 = 1 1 - 2
AND Bitwise AND and Shift 4h C[25:23]=010, C5 = 1 1 - 3
APCNT Angle Period Count Eh - 1 - 2
BR Branch Dh - 1
CNT Count 6h - 1 - 2
DADM64 Data Add Move 64 2h - 2
DJZ Decrement and Jump if -zero Ah P[7:6] = 10 1
ECMP Equality Compare 0h C[6:5] = 00 1
ECNT Event Count Ah P[7:6] = 01 1
MCMP Magnitude Compare 0h C[6] = 1 1
MOV32 Move 32 4h C[5] = 0 1 - 2
MOV64 Move 64 1h - 1
PCNT Pulse/Period Count 7h - 1
PWCNT Pulse Width Count Ah P[7:6]=11 1
RADM64 Register Add Move 64 3h - 1
RCNT Ratio Count Ah P[7:6]=00, P[0]=1 3
SBB Subtract with Borrow and Shift 4h C[25:23] =110 C[5] =1 1 - 3
SCMP Sequence Compare 0h C[6:5] = 01 1
SCNT Step Count Ah P[7:6] = 00, P[0] = 0 3
SHFT Shift Fh C[3]=0 1
SUB Subtract and Shift 4h C[25:23]=101, C[5] = 1 1 - 3
WCAP Software Capture Word Bh - 1
Software Capture Word and Event
WCAPE 8h - 1
Count
XOR Bitwise Exclusive-Or and Shift 4h C[25:23] , C[5] = 1 1 - 3
(1)
Cycles refers to the clock cycle of the N2HET module; which on most devices is VCLK2. (Check the device datasheet
description of clock domains to confirm). If the high resolution prescale value is set to /1, then this is also the same as the
number of HR clock cycles.
994
High-End Timer (N2HET) Module SPNU562–May 2014
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