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N2HET Control Registers

23.4.33 N2HET Pin Disable Register (HETPINDIS)

N2HET1: offset = FFF7 B894h; N2HET2: offset = FFF7 B994h

Figure 23-67. N2HET Pin Disable Register (HETPINDIS)

31 16

HETPINDIS

R/W-0

15 0

HETPINDIS

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-48. NHET Pin Disable Register (HETPINDIS) Field Descriptions

Bit Field Value Description

31-0 HETPINDIS n N2HET Pin Disable Bits

0 Logic low: No affect on the output buffer enable of the pin (is controlled by the value of the

HETDIR[n] bit).

1 Logic high: Output buffer of the pin is enabled if pin nDIS = 1, HET PIN ENA = 1 and HETDIR =

1, or else disabled if nDIS = 0 or HETDIR = 0 or HET PIN ENA = 0.

993

SPNU562–May 2014 High-End Timer (N2HET) Module

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