Datasheet

N2HET Control Registers www.ti.com
23.4.29 Suppression Filter Preload Register (HETSFPRLD)
N2HET1: offset = FFF7 B880h; N2HET2: offset = FFF7 B980h
Figure 23-63. Suppression Filter Preload Register (HETSFPRLD)
31 18 17 16
Reserved CCDIV
R-0 R/W-0
15 10 9 0
Reserved CPRLD
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-44. Suppression Filter Preload Register (HETSFPRLD) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Read returns 0. Writes have no effect.
17-16 CCDIV Counter Clock Divider
CCDIV determines the ratio between the counter clock and VCLK2.
0 CCLK = VCLK2
1h CCLK = VCLK2 / 2
2h CCLK = VCLK2 / 3
3h CCLK = VCLK2 / 4
15-10 Reserved 0 Read returns 0. Writes have no effect.
9-0 CPRLD Counter Preload Value
CPRLD contains the preload value for the counter clock.
23.4.30 Suppression Filter Enable Register (HETSFENA)
N2HET1: offset = FFF7 B884h; N2HET2: offset = FFF7 B984h
Figure 23-64. Suppression Filter Enable Register (HETSFENA)
31 16
HETSFENA
R/W-0
15 0
HETSFENA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-45. Suppression Filter Enable Register (HETSFENA) Field Descriptions
Bit Field Value Description
31-0 HETSFENA n Suppression Filter Enable Bits
Note: If the pin is configured as an output by the N2HET Direction Register (HETDIR), the filter
is automatically disabled independent on the bit in HETSFENA.
0 The input noise suppression filter for pin HET[n] is disabled.
1 The input noise suppression filter for pin HET[n] is enabled.
990
High-End Timer (N2HET) Module SPNU562–May 2014
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