Datasheet

121
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.17 DMA Controller
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
• Transfer blocks of data between external and internal data memories
• Restructure portions of internal data memory
• Continually service a peripheral
6.17.1 DMA Features
• 64-bit OCP protocol to perform bus master accesses
• INCR-4 64-bit burst accesses
• Multithreading architecture allowing data of two different channel transfers to be interleaved during nonburst
accesses
• 2-port configuration for parallel bus master
• Channels can be assigned to either high-priority queue or low-priority queue. Within each queue, fixed or round-
robin priorities can be serviced
• Built-in ECC generation and evaluation logic for internal RAM storing channel transfer information
• Supports multiple interrupt outputs for mapping to multiple interrupt controllers in multicore systems
• 48 requests can be mapped to any 32 channels
• Supports LE endianess
• External ECC Gen/Eval block of DMA support ECC generation for data transactions, and parity for address, and
control signals (following Cortex-R5F standard)
• 8 MPU regions
• Channel chaining capability
• Hardware and software DMA requests
• 8-, 16-, 32-, or 64-bit transactions supported
• Multiple addressing modes for source/destination (fixed, increment, offset)
• Auto-initiation
6.17.2 DMA Transfer Port Assignment
There are two ports, port A and port B attached to the DMA controller. When configuring a DMA channel
for a transfer, the application must also specify the port associated with the transfer source and
destination. Table 6-40 lists the mapping between each port and the resources. For example, if a transfer
is to be made from the the flash to the SRAM, the application will need configure the desired DMA
channel in the PARx register to select port A as the target for both the source and destination. If a transfer
is to be made from the SRAM to a peripheral or a peripheral memory, the application will need to
configure the desired DMA channel in the PARx register to select port A for read and port B for write.
Likewise, if a transfer is from a peripheral to the SRAM then the PARx will be configured to select port B
for read and port A for write.
Table 6-40. DMA Port Assignment
TARGET NAME ACCESS PORT OF DMA
Flash Port A
SRAM Port A
EMIF Port A
Flash OTP/ECC/EEPROM Port A
All other targets (peripherals, peripheral memories) Port B