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N2HET Control Registers www.ti.com
23.4.21 NHET Data Set Register (HETDSET)
N2HET1: offset = FFF7 B858h; N2HET2: offset = FFF7 B958h
Figure 23-55. N2HET Data Set Register (HETDSET)
31 16
HETDSET
R/WS-0
15 0
HETDSET
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 23-35. N2HET Data Set Register (HETDSET) Field Descriptions
Bit Field Value Description
31-0 HETDSET n This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write
sequence in a multitasking environment.
Bits written as a logic 1 set the same bit in the HETDOUT register; while bits written as logic 0
leave the same bit in HETDOUT unchanged. Reads from this address return the value of the
HETDOUT register.
0 Write: HETDOUT[n] is unchanged.
1 Write: HETDOUT[n] is set.
23.4.22 N2HET Data Clear Register (HETDCLR)
N2HET1: offset = FFF7 B85Ch; N2HET2: offset = FFF7 B95Ch
Figure 23-56. N2HET Data Clear Register (HETDCLR)
31 16
HETDCLR
R/WC-0
15 0
HETDCLR
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-36. N2HET Data Clear Register (HETDCLR) Field Descriptions
Bit Field Value Description
31-0 HETDCLR n This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modify-
write sequence in a multitasking environment.
Bits written as a logic 1 clear the same bit in the HETDOUT register; while bits written as logic 0
leave the same bit in HETDOUT unchanged. Reads from this address return the value of the
HETDOUT register.
0 Write: HETDOUT[n] is unchanged.
1 Write: HETDOUT[n] is cleared.
984
High-End Timer (N2HET) Module SPNU562–May 2014
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