Datasheet
N2HET Control Registers
www.ti.com
23.4.15 Request Enable Set Register (HETREQENS)
N2HET1: offset = FFF7 B83Ch; N2HET2: offset = FFF7 B93Ch
Figure 23-49. Request Enable Set Register (HETREQENS)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
REQ ENA 7 REQ ENA 6 REQ ENA 5 REQ ENA 4 REQ ENA 3 REQ ENA 2 REQ ENA 1 REQ ENA 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-29. Request Enable Set Register (HETREQENS) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Read returns 0. Writes have no effect.
7-0 REQ ENA n Request Enable Bits
0 Read: Returns the information that request line n is disabled.
Write: Writing a 0 has no effect.
1 Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n enables the N2HET request line n.
Note: The request line can trigger a DMA control packet (DMA channel), an HTU double control
packet (DCP) or both simultaneously. The HETREQDS register determines to which module(s)
the N2HET request line n is assigned.
Note: A disabled request line does not memorize old requests. So there are no pending
requests to service after enabling request line n.
23.4.16 Request Enable Clear Register (HETREQENC)
N2HET1: offset = FFF7 B840h; N2HET2: offset = FFF7 B940h
Figure 23-50. Request Enable Clear Register (HETREQENC)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
REQ DIS 7 REQ DIS 6 REQ DIS 5 REQ DIS 4 REQ DIS 3 REQ DIS 2 REQ DIS 1 REQ DIS 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-30. Request Enable Clear Register (HETREQENC) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Read returns 0. Writes have no effect.
7-0 REQ DIS n Request Disable Bits
0 Read: Returns the information that request line n is disabled.
Write: Writing a 0 has no effect.
1 Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n disables the N2HET request line n.
980
High-End Timer (N2HET) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated