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N2HET Control Registers

23.4.14 XOR Share Control Register (HETXOR)

N2HET1: offset = FFF7 B838h; N2HET2: offset = FFF7 B938h

Figure 23-48. XOR Share Control Register (HETXOR)

31 16

Reserved

R-0

15 14 13 12 11 10 9 8

XORSHARE31/30 XORSHARE29/28 XORSHARE27/26 XORSHARE25/24 XORSHARE23/22 XORSHARE21/20 XORSHARE19/18 XORSHARE17/16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

XORSHARE15/14 XORSHARE13/12 XORSHARE11/10 XORSHARE9/8 XORSHARE7/6 XORSHARE5/4 XORSHARE3/2 XORSHARE1/0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-28. XOR Share Control Register (HETXOR) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

15-0 XOR SHARE XOR Share Enable

n+1 / n

Enable the XOR-share of the same pin for two output HR structures. For example, if bit XOR

SHARE 1/0 is set, the pin HET[0] will then be commanded by a logical XOR of both HR

structures 0 and 1.

Note: If XOR share bits are used, pins not connected to HR structures (the odd number pin in

each pair) can be accessed as general inputs/outputs.

0 HR Output of HET[n+1] and HET[n] are not XOR shared

1 HR Output of HET[n+1] and HET[n] are XOR shared onto pin HET[n]

979

SPNU562–May 2014 High-End Timer (N2HET) Module

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