Datasheet

N2HET Control Registers

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23.4.13 HR Share Control Register (HETHRSH)

N2HET1: offset = FFF7 B834h; N2HET2: offset = FFF7 B934h

Figure 23-47. HR Share Control Register (HETHRSH)

31 16

Reserved

R-0

15 14 13 12 11 10 9 8

HRSHARE31/30 HRSHARE29/28 HRSHARE27/26 HRSHARE25/24 HRSHARE23/22 HRSHARE21/20 HRSHARE19/18 HRSHARE17/16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

HRSHARE15/14 HRSHARE13/12 HRSHARE11/10 HRSHARE9/8 HRSHARE7/6 HRSHARE5/4 HRSHARE3/2 HRSHARE1/0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-27. HR Share Control Register (HETHRSH) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

15-0 HR SHARE HR Share Bits

n+1 / n

Enables the share of the same pin for two HR structures. For example, if bit HR share 1/0 is

set, the pin HET[0] will then be connected to both HR input structures 0 and 1.

Note: If HR share bits are used, pins not connected to HR structures (the odd number pin in

each pair) can be accessed as general inputs/outputs.

0 HR Input of HET[n+1] and HET[n] are not shared.

1 HR Input of HET[n+1] and HET[n] are shared; both measure pin HET[n]

978

High-End Timer (N2HET) Module SPNU562–May 2014

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