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N2HET Control Registers

23.4.12 AND Share Control Register (HETAND)

N2HET1: offset = FFF7 B82Ch; N2HET2: offset = FFF7 B92Ch

Figure 23-46. AND Share Control Register (HETAND)

31 16

Reserved

R-0

15 14 13 12 11 10 9 8

ANDSHARE31/30 ANDSHARE29/28 ANDSHARE27/26 ANDSHARE25/24 ANDSHARE23/22 ANDSHARE21/20 ANDSHARE19/18 ANDSHARE17/16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

ANDSHARE15/14 ANDSHARE13/12 ANDSHARE11/10 ANDSHARE9/8 ANDSHARE7/6 ANDSHARE5/4 ANDSHARE3/2 ANDSHARE1/0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23-26. AND Share Control Register (HETAND) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

15-0 AND SHARE AND Share Enable

n+1 / n

Enable the AND sharing of the same pin for two HR structures. For example, if bit AND SHARE

1/0 is set, the pin HET[0] will then be commanded by a logical AND of both HR structures 0 and

Note: If HR AND SHARE bits are used, pins not connected to HR structures (the odd number

pin in each pair) can be accessed as general inputs/outputs.

0 HR Output of HET[n+1] and HET[n] are not AND shared

1 HR Output of HET[n+1] and HET[n] are AND shared onto pin HET[n]

977

SPNU562–May 2014 High-End Timer (N2HET) Module

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