Datasheet

www.ti.com N2HET Control Registers
23.4.9 Exception Control Register 2 (HETEXC2)
N2HET1: offset = FFF7 B820h; N2HET2: offset = FFF7 B920h
Figure 23-43. Exception Control Register 2 (HETEXC2)
31 16
Reserved
R-0
15 9 8
Reserved DEBUG STATUS
FLAG
R-0 R/WC-0
7 3 2 1 0
Reserved APCNT OVRFL APCNT UNRFL PRGM OVRFL
FLAG FLAG FLAG
R-0 R/WC-0 R/WC-0 R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 23-23. Exception Control Register 2 (HETEXC2) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Read returns 0. Writes have no effect.
8 DEBUG STATUS FLAG Debug Status Flag.
This flag is set when N2HET has stopped at a breakpoint. Also generates a debug
request to halt the ARM CPU.
0 Read: N2HET is either running, or stopped, flag cleared but not yet restarted.
Write: No effect.
1 Read: N2HET is stopped at a breakpoint.
Write: Clears the bit. To restart N2HET clear this bit and then restart the ARM CPU. The
N2HET and ARM CPU will start synchronously.
7-3 Reserved 0 Read returns 0. Writes have no effect.
2 APCNT OVRFL FLAG APCNT Overflow Flag
0 Read: Exception has not occurred since the flag was cleared.
Write: No effect.
1 Read: Exception has occurred since the flag was cleared.
Write: Clears the bit.
1 APCNT UNDFL FLAG APCNT Underflow Flag
0 Read: Exception has not occurred since the flag was cleared.
Write: No effect.
1 Read: Exception has occurred since the flag was cleared.
Write: Clears the bit.
0 PRGM OVERFL FLAG Program Overflow Flag
0 Read: Exception has not occurred since the flag was cleared.
Write: No effect.
1 Read: Exception has occurred since the flag was cleared
Write: Clears the bit.
975
SPNU562–May 2014 High-End Timer (N2HET) Module
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