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N2HET Control Registers www.ti.com
23.4.8 Exception Control Register 1 (HETEXC1)
N2HET1: offset = FFF7 B81Ch; N2HET2: offset = FFF7 B91Ch
Figure 23-42. Exception Control Register (HETEXC1)
31 25 24
Reserved APCNT OVRFL
ENA
R-0 R/W-0
23 17 16
Reserved APCNT UNRFL
ENA
R-0 R/W-0
15 9 8
Reserved PRGM OVRFL
ENA
R-0 R/W-0
7 3 2 1 0
Reserved APCNT OVRFL APCNT UNRFL PRGM OVRFL
PRY PRY PRY
R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-22. Exception Control Register 1 (HETEXC1) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Read returns 0. Writes have no effect.
24 APCNT OVRFL ENA APCNT Overflow Enable
0 APCNT overflow exception is not enabled.
1 Enables the APCNT overflow exception.
23-17 Reserved 0 Read returns 0. Writes have no effect.
16 APCNT UNRFL ENA APCNT Underflow Enable
0 APCNT underflow exception is not enabled.
1 Enables the APCNT underflow exception.
15-9 Reserved 0 Read returns 0. Writes have no effect.
8 PRGM OVRFL ENA Program Overflow Enable
0 The program overflow exception is not enabled.
1 Enables the program overflow exception.
7-3 Reserved 0 Read returns 0. Writes have no effect.
2 APCNT OVRFL PRY APCNT Overflow Exception Interrupt Priority
0 Exception priority level 2
1 Exception priority level 1
1 APCNT UNRFL PRY APCNT Underflow Exception Interrupt Priority
0 Exception priority level 2
1 Exception priority level 1
0 PRGM OVRFL PRY ProgramOverflow Exception Interrupt Priority
0 Exception priority level 2
1 Exception priority level 1
974
High-End Timer (N2HET) Module SPNU562–May 2014
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