Datasheet

www.ti.com N2HET Control Registers
23.4.3 N2HET Current Address Register (HETADDR)
N2HET1: offset = FFF7 B808h; N2HET2: offset = FFF7 B908h
Figure 23-37. N2HET Current Address (HETADDR)
31 16
Reserved
R-0
15 9 8 0
Reserved HETADDR
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-16. N2HET Current Address (HETADDR) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Read returns 0. Writes have no effect.
8-0 HETADDR N2HET Current Address
Read: Returns the current N2HET program address.
Write: Writes have no effect.
23.4.4 Offset Index Priority Level 1 Register (HETOFF1)
N2HET1: offset = FFF7 B80Ch; N2HET2: offset = FFF7 B90Ch
Figure 23-38. Offset Index Priority Level 1 Register (HETOFF1)
31 16
Reserved
R-0
15 6 5 0
Reserved OFFSET1
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-17. Offset Index Priority Level 1 Register (HETOFF1) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Read returns 0. Writes have no effect.
5-0 OFFSET1 HETOFF1[5:0] indexes the currently pending high-priority interrupt. Offset values and sources are listed
below and the interrupt encoding format is presented in Table 23-18.
Read: Read of these bits determines the pending N2HET interrupt.
Write: Writes have no effect.
Note: In any read operation mode, the corresponding flag (in the HETFLG) is also cleared. In Emulation
mode the corresponding flag is not cleared.
971
SPNU562–May 2014 High-End Timer (N2HET) Module
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