Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsEvaluation board

1191

N2HET Control Registers

www.ti.com

23.4 N2HET Control Registers

Table 23-13 summarizes all the N2HET registers. The base address for the control registers is

FFF7 B800h for N2HET1 and FFF7 B900h for N2HET2.

Table 23-13. N2HET Registers

Offset Acronym Register Description Section

00h HETGCR Global Configuration Register Section 23.4.1

04h HETPFR Prescale Factor Register Section 23.4.2

08h HETADDR NHET Current Address Register Section 23.4.3

0Ch HETOFF1 Offset Index Priority Level 1 Register Section 23.4.4

10h HETOFF2 Offset Index Priority Level 2 Register Section 23.4.5

14h HETINTENAS Interrupt Enable Set Register Section 23.4.6

18h HETINTENAC Interrupt Enable Clear Register Section 23.4.7

1Ch HETEXC1 Exception Control Register 1 Section 23.4.8

20h HETEXC2 Exception Control Register 2 Section 23.4.9

24h HETPRY Interrupt Priority Register Section 23.4.10

28h HETFLG Interrupt Flag Register Section 23.4.11

2Ch HETAND AND Share Control Register Section 23.4.12

34h HETHRSH HR Share Control Register Section 23.4.13

38h HETXOR HR XOR-Share Control Register Section 23.4.14

3Ch HETREQENS Request Enable Set Register Section 23.4.15

40h HETREQENC Request Enable Clear Register Section 23.4.16

44h HETREQDS Request Destination Select Register Section 23.4.17

4Ch HETDIR NHET Direction Register Section 23.4.18

50h HETDIN NHET Data Input Register Section 23.4.19

54h HETDOUT NHET Data Output Register Section 23.4.20

58h HETDSET NHET Data Set Register Section 23.4.21

5Ch HETDCLR NHET Data Clear Register Section 23.4.22

60h HETPDR NHET Open Drain Register Section 23.4.23

64h HETPULDIS NHET Pull Disable Register Section 23.4.24

68h HETPSL NHET Pull Select Register Section 23.4.25

74h HETPCR Parity Control Register Section 23.4.26

78h HETPAR Parity Address Register Section 23.4.27

7Ch HETPPR Parity Pin Register Section 23.4.28

80h HETSFPRLD Suppression Filter Preload Register Section 23.4.29

84h HETSFENA Suppression Filter Enable Register Section 23.4.30

8Ch HETLBPSEL Loop Back Pair Select Register Section 23.4.31

90h HETLBPDIR Loop Back Pair Direction Register Section 23.4.32

94h HETPINDIS NHET Pin Disable Register Section 23.4.33

968

High-End Timer (N2HET) Module SPNU562–May 2014

Submit Documentation Feedback