Datasheet

CAM
FIFO
FIFO
FIFO
FIFO
CPU0CorrectableError
CPUSCRCorrectableECCforDMA I/F
CPUSCRCorrectableECCforPS_SCR_MI/F
L2RAMWRMWCorrectableError
Lookup
FSM
ErrGen
ErrStat
ESM
CorrectableErrorCaptureBlock
CPUSCRUncorrectableECCforDMA I/F
CPUSCRUncorrectableECCforPS_SCR_MI/F
ErrGen
UncorrectableErrorCaptureBlock
UERR AddrReg
UERR AddrReg
ErrStat
ErrStat
EPCModule
CorrectableErrorEventSource
UnorrectableErrorEventSource
ch0
ch2
ch3
ch4
ch0
ch1
119
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
NOTE
The application can change the mapping of interrupt sources to the interrupt channels
through the interrupt channel control registers (CHANCTRLx) inside the VIM module.
6.16 ECC Error Event Monitoring and Profiling
This device includes an Error Profiling Controller (EPC) module. The main goal of this module is to enable
the system to tolerate a certain amount of ECC correctable errors on the same address repeatedly in the
memory system with minimal runtime overhead. Main features implemented in this device are described
below.
• Capture the address of correctable ECC faults from different sources (for example, CPU, L2RAM, Interconnect)
into a 16-entry Content Addressable Memory (CAM).
• For correctable faults, the error handling depends on the below conditions:
– if the incoming address is already in the 16-entry CAM, discard the fail. No error generated to ESM
– if the address is not in the CAM list, and the CAM has empty entries, add the address into the CAM list. In
addition, raise the error signal to the ESM group 1 if enabled.
– if the address is not in the CAM list, and the CAM has no empty entries, always raise a signal to the ESM
group 1.
• A 4-entry FIFO to store correctable error events and addresses for each IP interface.
• For uncorrectable faults of non-CPU access, capture the address and raise a signal to the ESM group 2.
• The CAM is implemented in memory mapped registers. The CPU can read and write to any entry for diagnostic
test as if a real CAM memory macro.
Figure 6-18. EPC Block Diagram