Datasheet

5 LSB address
code 00000
5 LSB address
code 11111
Interrupt enable
Interrupt condition
Interrupt condition
Interrupt enable
Interrupt
Flag 0
Interrupt
Flag 31
www.ti.com N2HET Functional Description
Table 23-12. Interrupt Sources and Corresponding Offset Values in Registers HETOFFx
Source No. Offset Value
no interrupt 0
Instruction 0, 32, 64... 1
Instruction 1, 33, 65... 2
: :
Instruction 31, 63, 95... 32
Program Overflow 33
APCNT underflow: 34
APCNT overflow 35
The instructions capable of generating interrupts are listed in Table 23-51.
Figure 23-27. Interrupt Functionality on Instruction Level
Each interrupt source is associated with a priority level (level 1 or level 2). When multiple interrupts with
the same priority level occur during the same loop resolution the lowest flag bit is serviced first.
In addition to the interrupts generated by the instructions the N2HET can generate three additional
exceptions:
• Program overflow
• APCNT underflow (see Section 23.3.1.2)
• APCNT overflow (see Section 23.3.1.3)
23.2.8 Hardware Priority Scheme:
If two or more software interrupts are pending on the same priority level, the offset value will show the one
with the highest priority. The interrupt with the highest priority is the one with the lower offset value. This
scheme is hard-wired in the offset encoder. See Figure 23-28.
961
SPNU562–May 2014 High-End Timer (N2HET) Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated